Silicon photonics · optoelectronic integration

One platform.
Two ways to use light.

We build both product lines on a single silicon photonics process. One moves data with light — interconnect PHY IP, optical I/O chiplets and co-packaged optical engines. The other computes with light — an all-interference optical architecture for Transformer inference.

Interconnect products → The compute architecture →
Optical arrays from 96×32 to 1024×1024 From sub-watt to 2 POPS First SoC tape-out Q3 2026
01 / Why now

Demand grows 10× a year.
Silicon grows 2×.

Since Transformer became the dominant paradigm in 2017, the workload changed shape: from static weights against dynamic inputs on small matrices, to dynamic weights against dynamic inputs on very large ones. Matrix size and data movement exploded together.

Process scaling will not close the gap. Electronic silicon is arriving at three walls at once — power, memory bandwidth, and interconnect — and none of them yields to another node shrink. Light holds order-of-magnitude margins on all three axes simultaneously: roughly 10× in operating frequency, 100× in transport speed, 100× in compute energy.

Power wallMemory wallInterconnect wall
AI compute demand Electronic chip performance
1,000,000× 10,000× 100× 1× Y0Y2 Y4Y6 10× / year 2× / year ~15,000× apart years from a common baseline

Indexed to Y0 = 1×, logarithmic scale.

02 / The shift

Light moves data first. Then it does the arithmetic.

The industry is midway through a two-step transition, and the two steps run on the same wafer process. We ship in the first and build in the second.

STAGE 01

Electronic

electrical transport · electrical compute

The installed base, arriving at its physical limit. Every further gain is bought with power.

STAGE 02

Optical interconnect

optical transport · electrical compute

Moving data with light. Co-packaged optics and optical I/O entered volume production across the industry in 2025–2026.

Engine 01 — we ship here
STAGE 03

Optical compute

optical transport · optical compute

Computing with light. Interference performs the matrix operation itself. The window is opening now.

Engine 02 — we build here
03 / Two engines

Not diversification. The same foundation, harvested twice.

A photonic compute chip needs an on-chip and die-to-die optical interconnect subsystem of its own. The PHY is not an unrelated side business — it is a required subsystem of the core product, productised early so it earns revenue and builds customer relationships ahead of the compute roadmap.

Engine 01 · Interconnect

Move data with light.

Silicon photonic PHY delivered the way silicon teams actually consume it — as IP you license, a chiplet you co-package, or a module you buy.

  • SerDes PHY IP for licensing and NRE co-design
  • Optical I/O chiplets for 2.5D / 3D integration
  • Co-packaged optical engines for switching and clusters
Interconnect products →
Engine 02 · Compute

Compute with light.

Our architecture performs the matrix operation as optical interference — and gets the nonlinearity from the same physics, with no separate activation stage.

  • Insertion loss and programming error stay O(1) as the array grows
  • Standard system interfaces — the software stack is unchanged
  • Compute density does not depend on an advanced node
The architecture →
200×
Reduction in energy per operation
Optical compute against an electronic baseline
O(1)
Insertion loss and programming error, independent of array size
vs O(N) for MZI / MRR / PCM arrays
<1 W
First photonic AI SoC, 6 mm × 6 mm, 180 nm
Tape-out scheduled 2026
180 nm
Mature node for first silicon — compute density is not node-bound
45 nm for the 1024×1024 generation
04 / Where it lands

Four places where a watt decides the product.

On-device inference, space electronics, embodied AI and cloud inference sit at four different points on the compute scale — and each of them is constrained today by something light relieves directly.

On-device · TOPS Space electronics · TOPS Embodied AI · POPS Cloud inference · EOPS
Engine 01 · Silicon photonic interconnect

Move data with light.

Optical I/O you can license as IP, co-package as a chiplet, or buy as a module — built on the same silicon photonics platform and the same device library as our compute silicon.

01 / The market decided already

This is an engineering and cost problem now, not a feasibility question.

Co-packaged optics and optical I/O left the research phase in 2025–2026. The leading vendors have shipped product, which settles the architectural argument and moves the contest to execution, yield and cost.

DevelopmentWhat it establishesYear
NVIDIA Spectrum-X / Quantum-X PhotonicsCo-packaged optics in a shipping switch platform2025
Broadcom Tomahawk 6102.4 Tbps switching silicon2025
Ayar Labs · Lightmatter optical I/OOptical I/O products in customer delivery2025–2026
02 / Products

Three ways in, one device library.

P1
IP licence

Silicon photonic SerDes PHY IP

Single-channel PAM4 optical transceiver PHY — modulator driver, TIA, clock recovery and the optical coupling structure — delivered as licensable IP for integration into your own die.

For AI ASIC and switch silicon teams. Licence plus NRE, so the engagement can start and deliver ahead of any tape-out of ours.

P2
Chiplet

Optical I/O chiplet

An optical I/O die for 2.5D and 3D heterogeneous integration, co-packaged with your main compute or switch die and speaking a standardised die-to-die protocol.

For large-die programmes where electrical SerDes has run out of bandwidth-per-watt and reach. Chip supply plus joint design.

P3
Module

Co-packaged optical engine

A co-packaged optical engine module for switching platforms and compute clusters, supplied as a qualified assembly rather than as silicon to be integrated.

For switch equipment vendors and AI datacentre integrators who want the optics as a unit with defined electrical and optical interfaces.

03 / Engagement

Four ways to work with us.

IP licence
One-time licence for the PHY IP, integrated into your die. Shortest path to silicon.
NRE co-design
Milestone-based engineering for a customised optical front-end against your interface and package.
Chiplet supply
Optical I/O die supplied for co-packaging, with joint integration and test support.
Module supply
Qualified co-packaged optical engines with defined electrical and optical interfaces.
Start a conversation →
Engine 02 · All-interference architecture

Interference is the operation.

The world’s first photonic Transformer computing architecture for large models. Not a faster multiplier — a different primitive. Optical interference performs the matrix operation and supplies the nonlinearity from the same physics, so there is no separate activation stage to build.

01 / The principle

Three properties, one mechanism.

Interference replaces multiply-accumulate
Optical interference is used directly as the network's basic operation, in place of the conventional linear MAC.
Nonlinearity comes free
Interference introduces nonlinearity naturally. No separate activation function — Softmax included — has to be implemented.
Learning capacity is provable
Random Fourier feature theory supplies the mathematical guarantee for the all-interference optical attention mechanism.
02 / Why it scales

Loss and error stop growing with the array.

Every previous optical computing scheme has run into the same ceiling: as the array grows, insertion loss and calibration error grow with it, and the optical signal-to-noise budget is consumed before the array is large enough to be commercially interesting. Our architecture holds both at O(1). Scalability and programmability hold simultaneously — which is the necessary condition for a commercial compute chip.

Drop in the engine.
Keep your stack.

A conventional edge SoC hangs a DSP and an NPU off the system bus. Ours replaces the NPU with the optical compute core and leaves everything else standard — DSP, CPU, I²C, SPI, GPIO, audio and video I/O. From the integrator's side the software stack and the board-level integration are unchanged; what changes is the engine doing the arithmetic.

No advanced node required.

Optical compute density is set by photonics, not by transistor pitch. First silicon runs on 180 nm. The 1024×1024 generation runs on 45 nm. Even the cloud inference part targets 7 nm — a node that is broadly available.

For customers this reads two ways at once: a cost structure that does not carry leading-edge wafer prices, and a supply chain that does not depend on leading-edge capacity.

03 / Silicon

Three generations.

Photonic AI SoC

The world’s first commercially manufacturable photonic AI SoC — a 96×32 optical MAC array integrated with a standard SoC fabric, with the light source integrated on package — which is what allows the product form to collapse from a board into a chip.

Target applications: on-device inference, space electronics.

High-throughput photonic processor

A 1024×1024 optical array on a mature 45 nm process, aimed at the compute and latency envelope embodied-AI platforms need but cannot get from a central compute platform today.

Target applications: embodied AI, edge clusters.

Cloud inference processor

The reticle-scale end of the roadmap, where the economics of inference — not training — decide which architecture wins. Inference already accounts for over 65% of global AI chip spending.

Target applications: cloud and cluster inference.

Applications

Where a watt decides
the product.

Four markets, four points on the compute scale. In each one, the constraint that blocks the product today is the constraint optical compute relieves.

TOPS
On-device AI

Constraint today

Millimetre-scale package and sub-watt power are hard gates, not preferences. Everything else is negotiable; these two are not.

What it needs

Compute that fits inside the thermal and volume budget of the device itself, with the light source integrated rather than fibre-attached.

Which generation

Gen 1 photonic AI SoC — 6 mm × 6 mm at under 1 W. This is where the energy advantage is easiest to demonstrate against a shipping part.

TOPS
Space electronics

Constraint today

Power and thermal budgets are extreme, and there is a standing requirement for radiation tolerance that silicon logic meets only at a cost.

What it needs

High compute per watt in a sealed thermal envelope, from a device physics that is not built on charge storage in the first place.

Which generation

Gen 1 photonic AI SoC. A natural fit rather than an adapted one — the operating regime is what the architecture is already optimised for.

POPS
Embodied AI

Constraint today

Two bottlenecks at once. The reflex layer runs on AI SoCs at roughly 5 TOPS/W, which caps endurance; the cognitive layer runs on central compute platforms at roughly 300 TOPS, which caps how capable the model can be. Response latency follows from both.

What it needs

Over 100 TOPS/W of efficiency, over 2 POPS of throughput, and single-digit picosecond compute latency — simultaneously, in a package a machine can carry.

Which generation

Gen 2, the 1024×1024 processor at a 2 POPS target. The hardware requirement and the architecture's capability curve line up closely here.

EOPS
Cloud inference

Constraint today

Inference already accounts for over 65% of global AI chip spending against 35% for training, and inference buyers are far more sensitive to energy and total cost of ownership than training buyers are.

What it needs

A change in cost structure, not a performance increment. Competing on training throughput is not the play; competing on cost per token is.

Which generation

Gen 3 cloud inference processor, where the target cost per unit of compute falls three orders of magnitude below first silicon.

Company

Engineers who rewrite the physics.
Scientists who tape out.

Optical computing has a characteristic failure mode: a scientist proposes the principle, an engineer implements it, and the two are related by addition. The boundary of the principle never gets corrected by the manufacturing constraint, and the result performs beautifully and cannot be produced.

01 / How we work

We work by multiplication, not addition.

The architecture is a product of that method. It did not begin as a theory looking for an application. It began with an engineering fact — arrays cannot be made large because insertion loss and programming error grow with N — and reconstructed the computing principle backwards from there until that fact stopped being true.

That is what “known engineering constraints, revised underlying principle” means in practice, and it is why the O(1) result exists at all.

02 / One platform

Why the two product lines belong together.

Both lines are built on the same silicon photonics platform and the same process window; they share one PDK and device library of modulators, detectors, couplers and waveguides; they need the same opto-electronic co-design capability across optical simulation, electrical drive, timing and signal integrity; they use identical fibre coupling, laser integration and opto-electronic packaging; and they are measured on the same high-speed optical test bench with the same calibration methodology.

One investment, amortised across two product lines — and a compute chip that needs the interconnect subsystem anyway.

Contact

Request an evaluation.

Tell us which side you are approaching from and what the constraint is. Technical enquiries reach an engineer, not a queue.

Interconnect enquiries
Tell us the channel rate, the protocol, the package form and the production window. IP, chiplet and module routes all start from the same conversation.
Compute enquiries
Tell us the model, the throughput and power envelope, and when you need to evaluate. First-silicon samples follow the 2026 tape-out.
Press
Figures, architecture diagrams and product imagery are available on request. Interview requests are welcome.

Detailed specifications and evaluation data are shared under NDA.